In operations of dynamic random access memories, when an input of a write-with-auto-precharge (hereinafter, referred to as “WTA”) or read-with-auto-precharge (hereinafter, referred to as “RTA”) command occurs, the memory is automatically precharged after performing the respective reading or writing operations.
FIG. 1 illustrates a general auto-precharge signal generation circuit of a semiconductor memory device in a block diagram. As shown in FIG. 1, the auto-precharge signal generation circuit 1 receives a period set signal TRASMIN, a first column address strobe signal CASP10<0> and an auto-precharge flag signal A10_AP and generates a first auto-precharge signal APCGPB<0> for automatically precharging a first bank BANK<0> (not shown). The period set signal TRASMIN is provided to define a period for executing a reading or writing operation to the first bank BANK<0> (not shown) in response to the RTA or WTA command and for generating the first auto-precharge signal APCGPB<0> that automatically precharges the first bank BANK<0> (not shown). The first column address strobe signal CASP10<0> is generated in a pulse form for the reading and writing operation to the first bank BANK<0> (not shown). The auto-precharge flag signal A10_AP is enabled when in a high level state for automatically precharging all banks of the semiconductor memory device.
The auto-precharge signal generation circuit 1 operates as shown in the timing diagram of FIG. 2.
Referring to FIG. 2, if the first column address strobe signal CASP10<0> is applied to the circuit in a pulse form and the auto-precharge signal goes into a high level state, then the first auto-precharge signal APCGPB<0> is subsequently generated with a pulse for automatically precharging the first bank BANK<0> (not shown) that has been read or written when the period set signal TRASMIN is enabled in a high level state.
However, the pulse of the first auto-precharge signal APCGPB<0> is even generated when there is an input of a pulse from second through fourth column address strobe signals CASP10<1>, CASP10<2> (not shown), CASP10<3> (not shown), as well as, the first column address strobe signal CASP10<0>. As a result a malfunction can occur when in the reading or writing operation modes of the semiconductor memory device.
In further detail about this problem, if the second column address strobe signal CASP10<1> succeeds the first column address strobe signal CASP10<0> (i.e., CASP10<1> is continuously applied to the auto-precharge signal generation circuit 1 after CASP10<0> is applied thereto), a second pulse of the first auto-precharge signal APCGPB<0> can be inadvertently generated while the period set signal TRASMIN is enabled in the high level state. However, as shown in FIG. 2, the second pulse of the first auto-precharge signal APCGPB<0> can be generated in an abnormal pattern due to insufficiency of a time margin from the period set signal TRASMIN, which results in hindering the auto-precharge signal generation circuit 1 from being reset. This phenomenon incurs malfunctions of the auto-precharge signal generation circuit 1 in the reading or writing operation.